Automated Testing Equipment (ATE) tools are devices often used to test electronic designs, such as designs of integrated circuit (IC) or application specific integrated circuit (ASIC) products. Scan-based testing is one method of using ATE devices, in which scan logic allows an internal sequential element of the IC, such as a flip-flop, to be to be controlled and observed during testing. Chains of flip-flops (or “flops”) are connected as “scan chains”, and when testing is performed, test vector data that is applied through the scan chain control the sequential state of the flip-flops. After application of the test vector, the response of the scan chains is shifted out of the flip-flops and compared against expected responses to determine whether or not the IC is functioning correctly.
The length of a test vector is equal to the length of longest scan chain, and a test clock is pulsed as many times as the longest scan chain length. This causes the flip-flops in the scan chain to shift bit by bit as the test vector value is applied through it. This shifting of test vectors causes flip-flops in the scan chain to toggle between logic 0 to 1 or between 1 and 0.
The toggle activity in the flip-flop is a major component for dissipating power on the IC. Therefore, an increase in the number of toggles during testing will translate into higher average test power during the scan-based test. This is significant, since higher average test power may cause thermal hot-spots, which can result in false defects due to thermal imbalance conditions on the IC chip.
An increase in localized switching can also result in higher peak test power, which causes IR drops in the power-grid during execution. This can create false defects due to un-factored IR drop conditions on the IC chip and can also cause burn out on the IC chip in extreme cases. Moreover, increased Average and Peak Test Power could result in false defects or yield loss, wherein a good chip is classified as bad chip.
The present invention is directed to approaches to accurately and efficiently calculate the switching activity (or “toggle count”) when test vectors are applied during manufacturing tests on ATE devices. By accurately calculating the number of flip-flops that toggles during each test clock cycle, one can estimate the power dissipation during testing activity. The toggle count information also helps in predicting power hot-spots on the chip.
One possible approach to calculate toggle information during testing is to perform scan shift simulation. For each scan clock pulse in the simulation, the vector is shifted bit by bit through the scan chain and the current content of the scan chain is shifted out via the scan chain output. These actions are performed for each scan cycle to obtain the simulation results. The main limitation of scan shift simulation approach is its excessive run time, since the run-time for this approach is almost proportional to the square of the length of the scan chain.
Another possible approach is to compare the power dissipated by two test vectors, such as the technique described in Sankaralingam et al., “Static Compaction Techniques to Control Scan Vector Power Dissipation”, VLSI Test Symposium, 2000 18th IEEE. This technique assigns weights to transitions in scan vectors based on their position in the chain. The weight assigned to a transition is the difference between the size of the scan chain and the position in the vector in which the transition occurs. The longer a transition travels through the scan chain before it reaches the scan out, the higher the switching activity. Then a sum of weighted transitions is calculated to estimate scan power of a test vector. The test vector with higher sum of weighted transitions is deemed to be dissipating higher test power.
The main limitation with this approach is that it calculates test power by analyzing test vectors using gross estimates, and therefore does not provide accurate toggle counts for each scan cycle. This approach does not account for scan chain structure in the design, the unbalanced scan chains and the padding bits, and it also does not account for presence of inverters in the scan chains. In addition, this technique cannot provide the load and unload toggle count at each test clock pulse and does not provide the total number of toggles in each flop. Moreover, this technique does not account for toggles that occur in overlapped scan due to shifting of unload bit from the unload vector and loading of load bit from the load vector. Therefore, this technique only provides a first order estimate of power dissipated by a scan vector and does not provide the actual transitions count per test clock cycle.
Embodiments of the present invention provide an improved approach for analyzing the test vectors to quickly and accurately calculate the switching activity at each test clock pulse (scan cycle). Without any degradation in quality of results, embodiments of the present invention significantly reduce the run time as compared to the existing approach than does an explicit scan shift simulation. According to some embodiments, load vector data and unload vector data are analyzed to determine toggle counts and switching activity, without requiring simulation to be performed.
Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims. Both the foregoing general description and the following detailed description are exemplary and explanatory, and are not intended to be limiting as to the scope of the invention.